1. Field of the Invention
This invention relates to logic simulators and, more particularly, to methods of reducing the number of component evaluations required during a logic simulation.
2. Prior Art
Simulation techniques for logic circuits are used to predict changes in the signal values of circuit output signals and internal signals as a function of changes in circuit input signals. A logic circuit is typically described as an interconnected set, or network, or net, of components, such as AND-gates, inverters, and flip-flops. A circuit description can be produced as a list of components or as a list of nets, called a netlist. When describing a circuit as a list of components, each component entry in the list typically includes the name of a component, its function, and a list of inputs and outputs. Each entry in a netlist describes one net which connects two or more component pins of various devices, descriptions of which are stored in a library file. The signal values of interest for a logic circuit are logic values (typically 0, 1 and a few other values) for the circuit's signals, rather than voltages, etc. Logic circuit simulation is usually done on a general-purpose digital computer, although special-purpose machines are increasingly being used.
Event-driven simulation is a common method of logic circuit simulation. An "event" is defined as a change in the signal value or logic value of a signal. When an event occurs, that is, when a signal value changes, all components for which that signal is an input signal are scheduled for reevaluation in an event-driven simulation system. These reevaluations may cause additional events which, in turn, cause more reevaluations.
Levelized simulation is a second commonly used method of logic simulation. In this method, the components are levelized, that is, the components of a circuit are arranged or ordered in such a way that one component precedes a second component if the one component produces a signal that is an input signal for a second component. The components can then be evaluated in order. Evaluating components in order results in a faster simulation, because unnecessarily repeated evaluations are avoided. There are cases where no such ordering is possible, for example in the case of a feedback loop where one component produces a signal that is an input signal for another component and the other component produces a signal that is an input signal to the first component. Other more complicated feedback loops are also encountered. In the case of feedback loops, special evaluation techniques are used.
A compiled logic-circuit simulator program, as distinguished from an interpreted simulator, converts a circuit description directly into a set of machine-language instructions. These instructions describe the logic functions and interconnection of the components of the circuit. Each component has associated with it a corresponding set of machine language instructions and a corresponding current-value entry in a circuit value table. In contrast, an interpretive simulator program contains a set of tables in which descriptions of the circuit elements are contained. The interpretive simulator operates directly on the set of tables without converting the circuit description to machine language instructions.
Levelized compiled code (LCC) simulation is a form of computed simulation which incorporates a logic circuit description within the program. First, a circuit is levelized, that is, all of the circuit components are ordered as described above. Then a computer program is generated which evaluates all of the components in order. The program is then compiled. During simulation, the program is executed once for each change in the input signals of a circuit. Because the logic circuit description is incorporated into the compiled program, this method results in faster simulations than can be achieved by programs which treat the circuit description as data elements.
A number of techniques for reducing simulation time have been developed to avoid evaluation of every component each time that a circuit input signal changes. Each circuit component can be tested prior to evaluation to determine whether any of its input signals have changed. Other methods rely on knowledge of particular logic circuits. For example, if a circuit is known to be synchronous and if the clock signals for that circuit are available, it is possible to avoid evaluations during inactive phases of the clock signals. For particular circuits, simulation models uniquely suited for simulation can be individually designed.